-----------------------------------------------------------------------------
--  LEON3 Demonstration design
--  Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
--  This file is a part of the GRLIB VHDL IP LIBRARY
--  Copyright (C) 2003 - 2008, Gaisler Research
--  Copyright (C) 2008, 2009, Aeroflex Gaisler
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License as published by
--  the Free Software Foundation; either version 2 of the License, or
--  (at your option) any later version.
--
--  This program is distributed in the hope that it will be useful,
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--  GNU General Public License for more details.
--
--  You should have received a copy of the GNU General Public License
--  along with this program; if not, write to the Free Software
--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
------------------------------------------------------------------------------


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.net.all;
use gaisler.can.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;

entity leon3mp is
  generic (
    fabtech : integer := CFG_FABTECH;
    memtech : integer := CFG_MEMTECH;
    padtech : integer := CFG_PADTECH;
    clktech : integer := CFG_CLKTECH;
    disas   : integer := CFG_DISAS;     -- Enable disassembly to console
    dbguart : integer := CFG_DUART;     -- Print UART on console
    pclow   : integer := CFG_PCLOW
    );
  port (
    miso     : in    std_logic;
    mosi     : out   std_logic;
    sck      : out   std_logic;
    spiwpn   : out   std_logic;
    spicsn   : out   std_logic;
    spirstn  : out   std_logic;
    sda1     : inout std_logic;
    scl1     : inout std_logic;
    sda2     : inout std_logic;
    scl2     : inout std_logic;
    sda_oled : inout std_logic;
    scl_oled : inout std_logic;
    resetn   : in    std_ulogic;
    clk      : in    std_ulogic;
    errorn   : out   std_ulogic;
    address  : out   std_logic_vector(18 downto 0);
    data     : inout std_logic_vector(31 downto 0);
    dsutx    : out   std_ulogic;        -- DSU tx data
    dsurx    : in    std_ulogic;        -- DSU rx data
--    dsuen     : in std_ulogic;
    dsubre   : in    std_ulogic;
    dsuact   : out   std_ulogic;
    txd1     : out   std_ulogic;        -- UART1 tx data
    rxd1     : in    std_ulogic;        -- UART1 rx data
    ramsn    : out   std_logic;
    ramoen   : out   std_logic;
    ramben   : out   std_logic_vector (3 downto 0);
    rwen     : out   std_logic;
    oen      : out   std_ulogic;
    writen   : out   std_ulogic;
--    read      : out std_ulogic;
    romsn    : out   std_logic;
    iosn     : out   std_logic;
    ramclk   : out   std_logic;
    gpio     : inout std_logic_vector(6 downto 0);  -- I/O port

    flash_byten : out std_logic;
    flash_rpn   : out std_logic;
    sram_pwrdwn : out std_logic;
    sram_gwen   : out std_logic;
    sram_adsc   : out std_logic;
    sram_adsp   : out std_logic;
    sram_adv    : out std_logic;

    can_txd : out std_logic;
    can_rxd : in  std_logic;

    emdio   : inout std_logic;          -- ethernet PHY interface
    etx_clk : in    std_ulogic;
    erx_clk : in    std_ulogic;
    erxd    : in    std_logic_vector(3 downto 0);
    erx_dv  : in    std_ulogic;
    erx_er  : in    std_ulogic;
    erx_col : in    std_ulogic;
    erx_crs : in    std_ulogic;
    etxd    : out   std_logic_vector(3 downto 0);
    etx_en  : out   std_ulogic;
    etx_er  : out   std_ulogic;
    emdc    : out   std_ulogic;
    tck     : in    std_ulogic := '0';
    tms     : in    std_ulogic := '0';
    tdi     : in    std_ulogic := '0';
    trst    : in    std_ulogic := '0';
    tdo     : out   std_ulogic
    );
end;

architecture rtl of leon3mp is

  constant blength   : integer := 12;
  constant fifodepth : integer := 8;

  constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
                                  CFG_GRETH+CFG_AHB_JTAG;
  constant maxahbm : integer := maxahbmsp;

  signal vcc, gnd   : std_logic_vector(4 downto 0);
  signal memi       : memory_in_type;
  signal memo       : memory_out_type;
  signal wpo        : wprot_out_type;
  signal sdi        : sdctrl_in_type;
  signal sdo        : sdram_out_type;
  signal led        : std_logic_vector(3 downto 0);
  signal sdo2, sdo3 : sdctrl_out_type;

  signal apbi  : apb_slv_in_type;
  signal apbo  : apb_slv_out_vector := (others => apb_none);
  signal ahbsi : ahb_slv_in_type;
  signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
  signal ahbmi : ahb_mst_in_type;
  signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);

  signal clkm, rstn, rstraw, pciclk, sdclkl, clkrc, plock : std_ulogic;
  signal cgi                                              : clkgen_in_type;
  signal cgo                                              : clkgen_out_type;
  signal u1i, u2i, dui                                    : uart_in_type;
  signal u1o, u2o, duo                                    : uart_out_type;

  signal irqi : irq_in_vector(0 to CFG_NCPU-1);
  signal irqo : irq_out_vector(0 to CFG_NCPU-1);

  signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
  signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);

  signal dsui : dsu_in_type;
  signal dsuo : dsu_out_type;

  signal ethi, ethi1, ethi2 : eth_in_type;
  signal etho, etho1, etho2 : eth_out_type;

  signal gpti : gptimer_in_type;
  signal gpto : gptimer_out_type;

  signal gpioi            : gpio_in_type;
  signal gpioo            : gpio_out_type;
  signal can_lrx, can_ltx : std_ulogic;

  signal spii : spi_in_type;
  signal spio : spi_out_type;

  signal spmi1 : spimctrl_in_type;
  signal spmo1 : spimctrl_out_type;

  signal i2ci1, i2ci2, i2ci_oled : i2c_in_type;
  signal i2co1, i2co2, i2co_oled : i2c_out_type;

  signal lclk, letx_clk : std_ulogic;

--signal tck, tms, tdi, tdo : std_ulogic;
  signal resetnl, clk2x, spw_clkl : std_ulogic;

  constant IOAEN : integer := CFG_CAN;

  constant sysfreq   : integer := (CFG_CLKMUL/CFG_CLKDIV)*20000;
  constant boardfreq : integer := 20000;

  attribute syn_isclock           : boolean;
  attribute syn_preserve          : boolean;
  attribute syn_isclock of clkrc  : signal is true;
  attribute syn_isclock of clkm   : signal is true;
  attribute syn_preserve of plock : signal is true;
  attribute syn_preserve of clkm  : signal is true;
  attribute syn_preserve of clkrc : signal is true;
begin

  flash_byten <= '1';
  flash_rpn   <= rstn;
  sram_pwrdwn <= '0';
  sram_gwen   <= '1';
  sram_adsc   <= '0';
  sram_adsp   <= '1';

----------------------------------------------------------------------
---  Reset and Clock generation  -------------------------------------
----------------------------------------------------------------------
  clkgen_0 : entity work.myRCOSC
    port map(clkrc);

  pll_0 : entity work.PLL_sys
    port map('1', clkrc, plock, clkm, '0');
  
  rstgen0 : rstn <= resetn and plock;

  p_seq_blink : process(clkm, rstn)
    variable counter : unsigned(24 downto 0);
  begin
    if rstn = '0' then
      led(0)  <= '0';
      counter := (others => '0');
    elsif rising_edge(clkm) then
      counter := counter + 1;
      led(0)  <= counter(counter'high);
    end if;
  end process;

----------------------------------------------------------------------
---  AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------

  ahb0 : ahbctrl                        -- AHB arbiter/multiplexer
    generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
                 rrobin  => CFG_RROBIN, ioaddr => CFG_AHBIO,
                 ioen    => 1, nahbm => maxahbm, nahbs => 8)
    port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);

----------------------------------------------------------------------
---  LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------

  l3 : if CFG_LEON3 = 1 generate
    cpu : for i in 0 to CFG_NCPU-1 generate
      u0 : leon3s                       -- LEON3 processor      
        generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
                     0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
                     CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
                     CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
                     CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
                     CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
        port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
                  irqi(i), irqo(i), dbgi(i), dbgo(i));
    end generate;

    errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
    gpio(0) <= dbgo(0).error;
    
    dsugen : if CFG_DSU = 1 generate
      dsu0 : dsu3                       -- LEON3 Debug Support Unit
        generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
                     ncpu   => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
        port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
      dsui.enable <= '1';
      dsubre_pad : inpad generic map (tech  => padtech) port map (not dsubre, dsui.break);
      dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
    end generate;
  end generate;

  nodsu : if CFG_DSU = 0 generate
    ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
  end generate;

  dcomgen : if CFG_AHB_UART = 1 generate
    dcom0 : ahbuart                     -- Debug UART
      generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
      port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
    dsurx_pad : inpad generic map (tech  => padtech) port map (dsurx, dui.rxd);
    dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
  end generate;
  nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;

----------------------------------------------------------------------
---  Memory controllers ----------------------------------------------
----------------------------------------------------------------------

  mctrl2 : if (CFG_MCTRL_LEON2 = 1) and (CFG_SSCTRL = 0) generate  -- LEON2 memory controller
    sr1 : mctrl generic map (hindex  => 0, pindex => 0, paddr => 0,
                             srbanks => 2, sden => CFG_MCTRL_SDEN, ram8 => CFG_MCTRL_RAM8BIT,
                             ram16   => CFG_MCTRL_RAM16BIT, invclk => CFG_MCTRL_INVCLK,
                             romaddr => 16#100#, rommask => 16#FFE#)
      port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
    sram_adv <= '1';
    ramben_pads : for i in 0 to 3 generate
      x : outpad generic map (tech => padtech)
        port map (ramben(i), memo.mben(3-i));
    end generate;
  end generate;

  mempads : if CFG_MCTRL_LEON2 = 1 generate  -- LEON2 memory controller
    addr_pad : outpadv generic map (width => 19, tech => padtech)
      port map (address, memo.address(20 downto 2));
    rams_pad : outpad generic map (tech => padtech)
      port map (ramsn, memo.ramsn(0));
    roms_pad : outpad generic map (tech => padtech)
      port map (romsn, memo.romsn(0));
    iosn_pad : outpad generic map (tech => padtech)
      port map (iosn, memo.iosn);
    oen_pad : outpad generic map (tech => padtech)
      port map (oen, memo.oen);
    rwen_pad : outpad generic map (tech => padtech)
      port map (rwen, memo.writen);
    roen_pad : outpad generic map (tech => padtech)
      port map (ramoen, memo.ramoen(0));
    wri_pad : outpad generic map (tech => padtech)
      port map (writen, memo.writen);

    bdr : for i in 0 to 3 generate
      data_pad : iopadv generic map (tech => padtech, width => 8)
        port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
                  memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
    end generate;

  end generate;

  memi.brdyn  <= '1'; memi.bexcn <= '1';
  memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10";

----------------------------------------------------------------------
-------------------------  AHB ROM -----------------------------------
----------------------------------------------------------------------

  bpromgen : if CFG_AHBROMEN /= 0 generate
    brom : entity work.ahbrom
      generic map (hindex => 7, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
      port map (rstn, clkm, ahbsi, ahbso(7));
  end generate;
  nobpromgen : if CFG_AHBROMEN = 0 generate
    ahbso(7) <= ahbs_none;
  end generate;

----------------------------------------------------------------------
---  APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------

  apb0 : apbctrl                        -- AHB/APB bridge
    generic map (hindex => 1, haddr => CFG_APBADDR)
    port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);

  ua1 : if CFG_UART1_ENABLE /= 0 generate
    uart1 : apbuart                     -- UART 1
      generic map (pindex   => 1, paddr => 1, pirq => 2, console => dbguart,
                   fifosize => CFG_UART1_FIFO)
      port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
    u1i.rxd  <= rxd1; u1i.extclk <= '0'; txd1 <= u1o.txd;
    u1i.ctsn <= '0';                    --rtsn1 <= u1o.rtsn;
  end generate;
  noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;

  irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
    irqctrl0 : irqmp                    -- interrupt controller
      generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
      port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
  end generate;
  irq3 : if CFG_IRQ3_ENABLE = 0 generate
    x : for i in 0 to CFG_NCPU-1 generate
      irqi(i).irl <= "0000";
    end generate;
    apbo(2) <= apb_none;
  end generate;

  gpt : if CFG_GPT_ENABLE /= 0 generate
    timer0 : gptimer                    -- timer unit
      generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
                   sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
                   nbits  => CFG_GPT_TW)
      port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
    gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
  end generate;
  notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;

  gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate  -- GR GPIO unit
    grgpio0 : grgpio
      generic map(pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 7)
      port map(rstn, clkm, apbi, apbo(11), gpioi, gpioo);

    pio_pads : for i in 2 to 6 generate
      pio_pad : iopad generic map (tech => padtech)
        port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
    end generate;
  end generate;

-----------------------------------------------------------------------
---  serial buses -----------------------------------------------------
-----------------------------------------------------------------------

  spimctrl1 : spimctrl
    generic map
    (hindex => 6, hirq => 6, faddr => 16#000#, fmask => 16#FFE#,
     ioaddr => 16#C00#, iomask => 16#FFF#, spliten => CFG_SPLIT,
     sdcard => 0, readcmd => 16#0B#, dummybyte => 1, dualoutput => 0,
     scaler => 1, altscaler => 1)
    port map
    (rstn, clkm, ahbsi, ahbso(6), spmi1, spmo1);

  spi_miso_pad : inpad generic map (tech => padtech)
    port map (miso, spmi1.miso);
  spi_mosi_pad : outpad generic map (tech => padtech)
    port map (mosi, spmo1.mosi);
  spi_sck_pad : outpad generic map (tech => padtech)
    port map (sck, spmo1.sck);
  spi_slvsel0_pad : outpad generic map (tech => padtech)
    port map (spicsn, spmo1.csn);

  gpio(1) <= spmo1.mosi;
  
-- write protect disabled
  spiwpn <= '1';

-- SPI flash is always active
  spirstn <= '1';

  i2c0 : i2cmst
    generic map (pindex => 12, paddr => 12, pmask => 16#FFF#, pirq => 9)
    port map (rstn, clkm, apbi, apbo(12), i2ci1, i2co1);

  i2c1 : i2cmst
    generic map (pindex => 13, paddr => 13, pmask => 16#FFF#, pirq => 11)
    port map (rstn, clkm, apbi, apbo(13), i2ci2, i2co2);
  
  i2c3 : i2cmst
    generic map (pindex => 14, paddr => 14, pmask => 16#FFF#, pirq => 12)
    port map (rstn, clkm, apbi, apbo(14), i2ci_oled, i2co_oled);
  
  i2c1_scl_pad : iopad
    generic map (tech => padtech)
    port map (scl1, i2co1.scl, i2co1.scloen, i2ci1.scl);
  i2c1_sda_pad : iopad
    generic map (tech => padtech)
    port map (sda1, i2co1.sda, i2co1.sdaoen, i2ci1.sda);
  
  i2c2_scl_pad : iopad
    generic map (tech => padtech)
    port map (scl2, i2co2.scl, i2co2.scloen, i2ci2.scl);
  i2c2_sda_pad : iopad
    generic map (tech => padtech)
    port map (sda2, i2co2.sda, i2co2.sdaoen, i2ci2.sda);

  i2c_oled_scl_pad : iopad
    generic map (tech => padtech)
    port map (scl_oled, i2co_oled.scl, i2co_oled.scloen, i2ci_oled.scl);
  i2c_oled_sda_pad : iopad
    generic map (tech => padtech)
    port map (sda_oled, i2co_oled.sda, i2co_oled.sdaoen, i2ci_oled.sda);


-----------------------------------------------------------------------
---  AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------

  ocram : if CFG_AHBRAMEN = 1 generate
    ahbram0 : ahbram generic map (hindex => 4, haddr => CFG_AHBRADDR,
                                  tech   => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
      port map (rstn, clkm, ahbsi, ahbso(4));
  end generate;
  nram : if CFG_AHBRAMEN = 0 generate ahbso(4) <= ahbs_none; end generate;

-----------------------------------------------------------------------
---  Boot message  ----------------------------------------------------
-----------------------------------------------------------------------

-- pragma translate_off
  x : report_version
    generic map (
      msg1 => "LEON3 for Fusion M1AFS1500 Embedded kit",
      msg2 => "GRLIB Version " & tost(LIBVHDL_VERSION/1000) & "." & tost((LIBVHDL_VERSION mod 1000)/100)
      & "." & tost(LIBVHDL_VERSION mod 100) & ", build " & tost(LIBVHDL_BUILD),
      msg3 => "Target technology: " & tech_table(fabtech) & ",  memory library: " & tech_table(memtech),
      mdel => 1
      );
-- pragma translate_on
end;
